1. Field of the Invention
The present invention relates generally to a vertical needle type probe card and more particularly to an improved vertical needle type probe card which can be manufactured at low cost and allow a shorter test time. The present invention also relates to a method of manufacturing such a vertical needle type probe card. Further, the present invention relates to a method of replacing a defective probe needle of the vertical needle type probe card. The present invention also relates to a test method of a wafer using the probe card.
2. Description of the Background Art
In manufacturing an IC, an LSI or the like, a plurality of wafer chips are generally produced on one board. Before these wafer chips are cut on a chip basis, a wafer test is carried out to check whether an individual chip is defective or not. In such a wafer test, a device called a prober is usually connected to a probe card, and a probe needle of the probe card comes into contact with a prescribed electrode (pad) of a semiconductor chip. After the probe needle comes into contact with the semiconductor chip, constant pressure (called needle pressure) is applied between the probe needle and the pad (this operation is called an overdrive). As a result of the overdrive, the probe needle is slid and moved on the pad surface, removing aluminum oxide of the pad surface. Thus, aluminum under aluminum oxide is electrically connected to the probe needle.
FIG. 24 is a cross sectional view of a probe card using a conventional cantilever type probe needle disclosed in Japanese Utility Model Laying-Open No. 57-146340. The probe card includes one printed wiring board 1 (hereinafter referred to as a board). An opening 2 is provided in the center of board 1. A plurality of probe needles 3 are radially provided at the lower surface of board 1 so that their tips reach prescribed positions in opening 2. The base of probe needle 3 and a contact portion for connecting a connector (not shown) provided at the end of board 1 are connected by a printed wiring or wire.
FIG. 25 shows the relationship between the displacement of the cantilever type probe needle and a force (F). In this specification, the probe needle displacement denotes the height of the tip of probe needle 3 from the lower surface of board 1, as shown in FIG. 26. In this specification, the force (F) denotes needle pressure (F) which is applied to probe needle 3 in its height direction at the time of the overdrive.
Referring to FIG. 25, a linear relationship is formed by the displacement of the probe needle and the force. In general, the overdrive of approximately 100 .mu.m applies the needle pressure of approximately a few grams (for example, 7 g) to probe needle 3. Thus, the pad and probe needle 3 are electrically connected to perform the wafer test.
The relative positions of probe needle 3 and the pad are essential in each of longitudinal, lateral and height directions. For each direction, the precision of approximately .+-.10 .mu.m is required. A high density IC which will be developed from now on should demand a much stricter precision. At present, the relative positions of the probe needle and the pad are adjusted by hand. In this case, it is difficult to adjust the height of the probe needle (distance of the tip of the probe needle from the lower surface of the board).
In order to test a memory IC, a method called a simultaneous test is usually employed to simultaneously test a plurality of memory IC chips on a wafer. In the simultaneous test, probe needles usually come into contact with a total of 2.times.8=16 pads. In short, referring to FIG. 24, one row of the cantilever type probe needles comes into contact with 1 row.times.8 ICs and another row of the probe needles comes into contact with 1 row.times.8 ICs, with a total of 2.times.8 memory IC chips tested simultaneously by the probe needles on the both sides.
It is assumed here that one wafer has such number and arrangement of IC chips that the tests of all the IC chips are completed after 20 times of the 2.times.8 simultaneous tests. In this case, the numbers of the 4.times.4 simultaneous tests and the 4.times.8 simultaneous tests are smaller than the 2.times.8 simultaneous tests, as described below.
In the case of the 2.times.8 simultaneous test, 20 times/wafer
in the case of the 4.times.4 simultaneous test, 15 times/wafer (-25%) PA1 in the case of the 4.times.8 simultaneous test, 10 times/wafer (-50%) PA1 tip diameter of the probe needle: about 30 .mu.m.phi. PA1 pitch of the probe needle: about 100 .mu.m PA1 number of the probe needle: about 300 pieces/row PA1 positional precision of the probe needle: about .+-.10 .mu.m
The more the number of chips to be tested simultaneously as in the case of 4.times.8=32 chips, the smaller the number of the test times. For the same number of the simultaneous tests, the test numbers are smaller in the 4.times.4 test than in the 2.times.8 test. It can be understood considering the arrangement of a plurality of memory IC chips on one wafer.
The smaller number of the test times means a shorter test time per wafer. The data above indicates that reduction of the test time by 25% or 50% is possible simply through modification of the probe card structure.
With the reduction of the test time, the time for the test process is shortened and therefore quick delivery of products becomes possible. Further, production is increased by 25% or 50% with the same number of the testers. Therefore, it is a great task for those of who carry out the wafer tests to increase the number of chips to be tested simultaneously by a probe card.
Both of the 2.times.8 structure and the 4.times.4 structure which allow the simultaneous test of 16 chips do not require modification of the tester. Therefore, the 4.times.4 structure which allows a shorter test time should have been realized by now. However, the 4.times.4 structure in which two stages of the cantilever type probe needles are placed on both sides as shown in FIG. 27 has not been realized. Although this type of the 4.times.4 structure can be manufactured in principle, maintenance such as adjustment of longitudinal, lateral and height positions and repair after each test is very complicated and difficult, resulting in the maintenance cost per needle several times higher.
For example, the difficulty of adjustment would be readily understood if the precision of the probe needle is indicated by numerical values. The probe needle specification is as follows.
In short, in the case of the 4.times.4 simultaneous test, there are about 300 needles in one row. Let us consider the two inner rows of the probe needles which are longer with reference to FIG. 27. In this case, it is very difficult to adjust the longitudinal, lateral and height positions of the probe needle so that the positional precision of the tip of the probe needle is always about .+-.10 .mu.m. In this present situation, therefore, the 2.times.8 simultaneous test method is employed by the probe card which has only the two outer rows.
In recent years, the degree of integration has greatly be improved from 16 M to 64 M and to 256 M especially in a DRAM memory IC, and it causes a longer test time which is an obstacle in the IC production line. Therefore, reduction in the test time is immediately required.
The structures such as 4.times.4, 4.times.8 and n (at least 4).times.m which are effective in reducing the test time have been studied for practical use by introducing a probe card (hereinafter referred to as a vertical needle type probe card) which uses a probe needle called a vertical needle.
FIG. 28 is a cross sectional view of a conventional vertical needle type probe card described in NIKKEI MICRODEVICES, September 1996, pp. 101-106. Referring to FIG. 28, a pin 4 is arranged in a vertical direction through a hole in a guide plate 6. The end of pin 4 is arranged in an arbitrary manner. A wafer is vertically moved from below toward above to contact pin 4. Since pin 4 functions as a spring, a load is applied to the pin end when the pin is retrieved. Since the conventional vertical needle type probe card has been described to this extent, its structure and the method of manufacturing thereof are not well known.